Datasheet

V850ES/JG3 CHAPTER 28 ON-CHIP DEBUG FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 755 of 870
Sep 30, 2010
Figure 28-4. Memory Spaces Where Debug Monitor Programs Are Allocated
CSI0/UART receive
interrupt vector (4 bytes)
Reset vector
(4 bytes)
Interrupt vector for debugging
(4 bytes)
(2 KB)
Security ID area
(10 bytes)
: Debugging area
Note 1
Note 2
Internal ROM
(16 bytes)
Access-prohibited area
Internal RAM
Internal ROM
area
Internal RAM
area
Note 3
0000000H
0000060H
0000070H
0000290H
3FFEFFFH
3FFEFF0H
Notes 1. Address values vary depending on the product.
Internal ROM Size Address Value
μ PD70F3739 384 KB 005F800H to 005FFFFH
μ PD70F3740 512 KB 007F800H to 007FFFFH
μ PD70F3741 768 KB 00BF800H to 00BFFFFH
μ PD70F3742 1024 KB 00FF800H to 00FFFFFH
2. This is the address when CSIB0 is used. It starts at 00002F0H when CSIB3 is used, and at 0000310H
when UARTA0 is used.
3. Address values vary depending on the product.
Internal ROM Size Address Value
μ PD70F3739 32 KB 3FF7000H
μ PD70F3740 40 KB 3FF5000H
μ PD70F3741
μ PD70F3742
60 KB 3FF0000H