Datasheet

V850ES/JG3 CHAPTER 3 CPU FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 61 of 870
Sep 30, 2010
3.4.8 Cautions
(1) Registers to be set first
Be sure to set the following registers first when using the V850ES/JG3.
• System wait control register (VSWC)
• On-chip debug mode register (OCDM)
• Watchdog timer mode register 2 (WDTM2)
After setting the VSWC, OCDM, and WDTM2 registers, set the other registers as necessary.
When using the external bus, set each pin to the alternate-function bus control pin mode by using the port-related
registers after setting the above registers.
(a) System wait control register (VSWC)
The VSWC register controls wait of bus access to the on-chip peripheral I/O registers.
Three clocks are required to access an on-chip peripheral I/O register (without a wait cycle). The V850ES/JG3
requires wait cycles according to the operating frequency. Set the following value to the VSWC register in
accordance with the frequency used.
The VSWC register can be read or written in 8-bit units (address: FFFFF06EH, default value: 77H).
Operating Frequency (fCLK) Set Value of VSWC Number of Waits
32 kHz ≤ fCLK < 16.6 MHz 00H 0 (no waits)
16.6 MHz ≤ fCLK < 25 MHz 01H 1
25 MHz ≤ fCLK ≤ 32 MHz 11H 2
(b) On-chip debug mode register (OCDM)
For details, see CHAPTER 28 ON-CHIP DEBUG FUNCTION.
(c) Watchdog timer mode register 2 (WDTM2)
The WDTM2 register sets the overflow time and the operation clock of watchdog timer 2.
Watchdog timer 2 automatically starts in the reset mode after reset is released. Write the WDTM2 register to
activate this operation.
For details, refer to CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2.