Datasheet

V850ES/JG3 CHAPTER 28 ON-CHIP DEBUG FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 753 of 870
Sep 30, 2010
Table 28-3. Wiring Between V850ES/JG3 and MINICUBE2
Pin Configuration of MINICUBE2 (QB-MINI2) With CSIB0-HS With CSIB3-HS With UARTA0
Signal Name I/O Pin Function Pin Name
Pin
No.
Pin Name
Pin
No.
Pin Name
Pin
No.
SI/RxD Input
Pin to receive commands and data from
V850ES/JG3
P41/SOB0 23 P911/SOB3 54 P30/TXD0 25
SO/TxD Output
Pin to transmit commands and data to
V850ES/JG3
P40/SIB0 22 P910/SIB3 53 P31/RXD0 26
SCK Output
Clock output pin for 3-wire serial
communication
P42/SCKB0 24 P912/SCKB3 55 Not needed
−
CLK Output Clock output pin Not needed
−
Not needed
−
Not needed
−
RESET_OUT Output Reset output pin to V850ES/JG3 RESET 14 RESET 14 RESET 14
FLMD0 Output
Output pin to set V850ES/JG3 to debug
mode or programming mode
FLMD0 8 FLMD0 8 FLMD0 8
FLMD1 Output Output pin to set programming mode PDL5/FLMD1 76 PDL5/FLMD1 76 PDL5/FLMD1 76
HS Input
Handshake signal for CSI0 + HS
communication
PCM0/WAIT 61 PCM0/WAIT 61 Not needed
−
VSS 11 VSS 11 VSS 11
AVSS 2 AVSS 2 AVSS 2
GND
−
Ground
EV
SS
33,
69
EV
SS
33,
69
EV
SS
33,
69
RESET_IN Input Reset input pin on the target system
28.2.2 Maskable functions
Only reset signals can be masked.
The maskable functions with the debugger (ID850QB) and the corresponding V850ES/JG3 functions are listed below.
Table 28-4. Maskable Functions
Maskable Functions with ID850QB Corresponding V850ES/JG3 Functions
NMI0
−
NMI1
−
NMI2
−
STOP
−
HOLD
−
RESET Reset signal generation by RESET pin input
WAIT
−