Datasheet

V850ES/JG3 CHAPTER 28 ON-CHIP DEBUG FUNCTION

R01UH0015EJ0300 Rev.3.00 Page 750 of 870

Sep 30, 2010

OCDM0

Operation mode

OCDM 0 0 0 0 0 0 OCDM0

After reset: 01H

Note

R/W Address: FFFFF9FCH

When DRST pin is low:

Normal operation mode (in which a pin that functions alternately as an

on-chip debug function pin is used as a port/peripheral function pin)

When DRST pin is high:

On-chip debug mode (in which a pin that functions alternately as an

on-chip debug function pin is used as an on-chip debug mode pin)

Selects normal operation mode (in which a pin that functions alternately

as on-chip debug function pin is used as a port/peripheral function pin) and

disconnects the on-chip pull-down resistor of the P05/INTP2/DRST pin.

< >

Note RESET input sets this register to 01H. After reset by the WDT2RES signal, clock monitor (CLM), or low-

voltage detector (LVI), however, the value of the OCDM register is retained.

Cautions 1. When using the DDI, DDO, DCK, and DMS pins not as on-chip debug pins but as port pins

after external reset, any of the following actions must be taken.

• Input a low level to the P05/INTP2/DRST pin.

• Set the OCDM0 bit. In this case, take the following actions.

<1> Clear the OCDM0 bit to 0.

<2> Fix the P05/INTP2/DRST pin to low level until <1> is completed.

2. The DRST pin has an on-chip pull-down resistor. This resistor is disconnected when the

OCDM0 flag is cleared to 0.

OCDM0 flag

(1: Pull-down ON, 0: Pull-down OFF)

10 to 100 kΩ

(30 kΩ (TYP.))

DRST