Datasheet

V850ES/JG3 CHAPTER 27 FLASH MEMORY
R01UH0015EJ0300 Rev.3.00 Page 740 of 870
Sep 30, 2010
(4) RESET pin
When the reset signals of the dedicated flash programmer are connected to the RESET pin that is connected to the
reset signal generator on-board, a conflict of signals occurs. To avoid the conflict of signals, isolate the connection
to the reset signal generator.
When a reset signal is input from the user system in the flash memory programming mode, the programming
operation will not be performed correctly. Therefore, do not input signals other than the reset signals from the
dedicated flash programmer.
Figure 27-14. Conflict of Signals (RESET Pin)
V850ES/JG3
RESET
Dedicated flash programmer
connection pin
Reset signal generator
Conflict of signals
Output pin
In the flash memory programming mode, the signal the reset signal generator
outputs conflicts with the signal the dedicated flash programmer outputs.
Therefore, isolate the signals on the reset signal generator side.
(5) Port pins (including NMI)
When the system shifts to the flash memory programming mode, all the pins that are not used for flash memory
programming are in the same status as that immediately after reset. If the external device connected to each port
does not recognize the status of the port immediately after reset, pins require appropriate processing, such as
connecting to V
DD via a resistor or connecting to VSS via a resistor.
(6) Other signal pins
Connect X1, X2, XT1, XT2, and REGC in the same status as that in the normal operation mode.
During flash memory programming, input a low level to the DRST pin or leave it open. Do not input a high level.
(7) Power supply
Supply the same power (V
DD, VSS, EVDD, EVSS, AVREF0, AVREF1, AVSS) as in normal operation mode.