Datasheet

V850ES/JG3 CHAPTER 27 FLASH MEMORY
R01UH0015EJ0300 Rev.3.00 Page 738 of 870
Sep 30, 2010
Table 27-8. Relationship Between FLMD0 and FLMD1 Pins and Operation Mode When Reset Is Released
FLMD0 FLMD1 Operation Mode
0 Don’t care Normal operation mode
VDD 0 Flash memory programming mode
VDD VDD Setting prohibited
(3) Serial interface pin
The following shows the pins used by each serial interface.
Table 27-9. Pins Used by Serial Interfaces
Serial Interface Pins Used
UARTA0 TXDA0, RXDA0
CSIB0 SOB0, SIB0, SCKB0
CSIB3 SOB3, SIB3, SCKB3
CSIB0 + HS SOB0, SIB0, SCKB0, PCM0
CSIB3 + HS SOB3, SIB3, SCKB3, PCM0
When connecting a dedicated flash programmer to a serial interface pin that is connected to another device on-
board, care should be taken to avoid conflict of signals and malfunction of the other device.
(a) Conflict of signals
When the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to
another device (output), a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to
the other device or set the other device to the output high-impedance status.
Figure 27-12. Conflict of Signals (Serial Interface Input Pin)
V850ES/JG3
Input pin
Conflict of signals
Dedicated flash programmer
connection pins
Other device
Output pin
In the flash memory programming mode, the signal that the dedicated flash
programmer sends out conflicts with signals another device outputs.
Therefore, isolate the signals on the other device side.