Datasheet

V850ES/JG3 CHAPTER 27 FLASH MEMORY
R01UH0015EJ0300 Rev.3.00 Page 735 of 870
Sep 30, 2010
27.4.4 Selection of communication mode
In the V850ES/JG3, the communication mode is selected by inputting pulses (12 pulses max.) to the FLMD0 pin after
switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated flash programmer.
The following shows the relationship between the number of pulses and the communication mode.
Figure 27-8. Selection of Communication Mode
V DD
V DD
RESET (input)
FLMD1 (input)
FLMD0 (input)
RXDA0 (input)
TXDA0 (output)
V SS
V DD
V SS
V DD
V SS
V DD
V SS
V DD
V SS
V DD
V SS
(Note)
Power on
Oscillation
stabilized
Communication
mode selected
Flash control command communication
(erasure, write, etc.)
Reset
released
Note The number of clocks is as follows depending on the communication mode.
FLMD0 Pulse Communication Mode Remarks
0 UARTA0 Communication rate: 9,600 bps (after reset), LSB first
8 CSIB0 V850ES/JG3 performs slave operation, MSB first
9 CSIB3 V850ES/JG3 performs slave operation, MSB first
11 CSIB0 + HS V850ES/JG3 performs slave operation, MSB first
12 CSIB3 + HS V850ES/JG3 performs slave operation, MSB first
Other RFU Setting prohibited
Caution When UARTA0 is selected, the receive clock is calculated based on the reset command sent
from the dedicated flash programmer after receiving the FLMD0 pulse.