Datasheet

V850ES/JG3 CHAPTER 27 FLASH MEMORY
R01UH0015EJ0300 Rev.3.00 Page 730 of 870
Sep 30, 2010
Table 27-6. Wiring of Flash Writing Adapter for V850ES/JG3 (FA-100GC-8EU-A) (1/2)
Flash Programmer (PG-FP4)
Connection Pins
When CSIB0 + HS Is
Used
When CSIB0 Is Used When UARTA0 Is Used
Signal
Name
I/O Pin Function
Pin Name
on FA
Board
Pin Name Pin
No.
Pin Name Pin
No.
Pin Name Pin
No.
SI/RxD Input Receive signal SI P41/SOB0/SCL01 23 P41/SOB0/SCL01 23 P30/TXDA0/SOB4 25
SO/TxD Output Transmit signal SO P40/SIB0/SDA01 22 P40/SIB0/SDA01 22 P31/RXDA0/INTP7/
SIB4
26
SCK Output Transfer clock SCK P42/SCKB0 24 P42/SCKB0 24 Not necessary
−
X1 Not necessary
−
Not necessary
−
Not necessary
−
CLK Output Clock to
V850ES/JG3
X2 Not necessary
−
Not necessary
−
Not necessary
−
/RESET Output Reset signal /RESET RESET 14 RESET 14 RESET 14
FLMD0 Output Write voltage FLMD0 FLMD0 8 FLMD0 8 FLMD0 8
FLMD1 Output Write voltage FLMD1 PDL5/AD5/FLMD1 76 PDL5/AD5/FLMD1 76 PDL5/AD5/FLMD1 76
HS Input Handshake
signal of CSI0
+ HS
communication
RESERVE /
HS
PCM0/WAIT 61 Not necessary
−
Not necessary
−
VDD 9 VDD 9 VDD 9
EVDD 34,
70
EVDD 34,
70
EVDD 34,
70
AVREF0 1 AVREF0 1 AVREF0 1
VDD
−
VDD voltage
generation/
voltage monitor
VDD
AV
REF1 5 AVREF1 5 AVREF1 5
VSS 11 VSS 11 VSS 11
AVSS 2 AVSS 2 AVSS 2
GND
−
Ground GND
EV
SS 33,
69
EVSS 33,
69
EVSS 33,
69
Cautions 1. Be sure to connect the REGC pin to GND via a 4.7
μ F (recommended value) capacitor.
2. A clock cannot be supplied from the CLK pin of the flash programmer. Create an oscillator on the
board and supply the clock from that oscillator.