Datasheet

V850ES/JG3 CHAPTER 27 FLASH MEMORY
R01UH0015EJ0300 Rev.3.00 Page 729 of 870
Sep 30, 2010
(3) CSIB0 + HS, CSIB3 + HS
Serial clock: 2.4 kHz to 2.5 MHz (MSB first)
Figure 27-5. Communication with Dedicated Flash Programmer (CSIB0 + HS, CSIB3 + HS)
V850ES/JG3
V
DD
V SS
RESET
SOB0, SOB3
SIB0, SIB3
SCKB0, SCKB3
PCM0
V DD
FLMD1 FLMD1
Note
GND
RESET
SI
SO
SCK
HS
FLMD0 FLMD0
Dedicated flash
programmer
Note Connect the FLMD1 pin to the flash programmer or connect to a GND via a pull-down resistor on the board.
The dedicated flash programmer outputs the transfer clock, and the V850ES/JG3 operates as a slave.
When the PG-FP4 is used as the dedicated flash programmer, it generates the following signals to the V850ES/JG3.
For details, refer to the PG-FP4 User’s Manual (U15260E).
Table 27-5. Signal Connections of Dedicated Flash Programmer (PG-FP4)
PG-FP4 V850ES/JG3 Processing for Connection
Signal Name I/O Pin Function Pin Name UARTA0
CSIB0,
CSIB3
CSIB0 + HS,
CSIB3 + HS
FLMD0 Output Write enable/disable FLMD0
FLMD1 Output Write enable/disable FLMD1
Note 1 Note 1 Note 1
VDD
−
VDD voltage generation/voltage monitor VDD
GND
−
Ground VSS
CLK Output Clock output to V850ES/JG3 X1, X2 ×
Note 2
×
Note 2
×
Note 2
RESET Output Reset signal RESET
SI/RxD Input Receive signal
SOB0, SOB3/
TXDA0
SO/TxD Output Transmit signal
SIB0, SIB3/
RXDA0
SCK Output Transfer clock SCKB0, SCKB3
×
HS Input
Handshake signal for CSIB0 + HS, CSIB3
+ HS communication
PCM0
× ×
Notes 1. Wire these pins as shown in Figure 27-6, or connect then to GND via pull-down resistor on board.
2. Clock cannot be supplied via the CLK pin of the flash programmer. Create an oscillator on board and supply
the clock.
Remark
: Must be connected.
×: Does not have to be connected.