Datasheet

V850ES/JG3 CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI)
R01UH0015EJ0300 Rev.3.00 Page 712 of 870
Sep 30, 2010
24.5 RAM Retention Voltage Detection Operation
The supply voltage and detected voltage are compared. When the supply voltage drops below the detected voltage
(including on power application), the RAMS.RAMF bit is set to 1.
Figure 24-4. Operation Timing of RAM Retention Voltage Detection Function
Supply voltage (V DD )
2.0 V
(minimum RAM
retention voltage)
RESET pin
RAMS.RAMF bit
Initialize RAM
(RAMF bit is also cleared)
When power application,
RAMF bit is set
RAM data
is not retained
RAMF bit = 0 is retained regardless
of RESET pin if V
DD > 2.0 V
Initialize RAM
(RAMF bit is also cleared)
V
DD < 2.0 V detected
Set RAMF bit
RAM data is
not retained
Remarks 1. The RAMF bit is set to 1 if the supply voltage drops under the minimum RAM retention voltage
(2.0 V (TYP.)).
2. The RAMF bit operates regardless of the RESET pin status.