Datasheet

V850ES/JG3 CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI)
R01UH0015EJ0300 Rev.3.00 Page 709 of 870
Sep 30, 2010
(2) Low-voltage detection level select register (LVIS)
The LVIS register is used to select the level of low voltage to be detected.
This register can be read or written in 8-bit or 1-bit units.
After reset: Note R/W Address: FFFFF891H
7 6 5 4 3 2 1 0
LVIS 0 0 0 0 0 0 0 LVIS0
LVIS0 Detection level
0 2.95 V (TYP.) ±0.10 V
1 Reserved (setting prohibited)
Note Reset by low-voltage detection: Retained
Reset due to other source: 00H
Cautions 1. This register cannot be written until a reset request due to something other than
low-voltage detection is generated after the LVIM.LVION and LVIM.LVIMD bits are
set to 1.
2. Be sure to clear bits 7 to 1 to “0”.
(3) Internal RAM data status register (RAMS)
The RAMS register is a special register. This can be written only in a special combination of sequences (see 3.4.7
Special registers).
This register is a flag register that indicates whether the internal RAM is valid or not.
This register can be read or written in 8-bit or 1-bit units.
The set/clear conditions for the RAMF bit are shown below.
• Setting conditions: Detection of voltage lower than specified level
Set by instruction
• Clearing condition: Writing of 0 in specific sequence
After reset: 01H
Note
R/W Address: FFFFF892H
7 6 5 4 3 2 1 <0>
RAMS 0 0 0 0 0 0 0 RAMF
RAMF Internal RAM voltage detection
0 Voltage lower than RAM retention voltage is not detected.
1 Voltage lower than RAM retention voltage is detected.
Note This register is reset only when a voltage drop below the RAM retention voltage is detected.