Datasheet

V850ES/JG3 CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI)
R01UH0015EJ0300 Rev.3.00 Page 708 of 870
Sep 30, 2010
24.3 Registers
The low-voltage detector is controlled by the following registers.
• Low-voltage detection register (LVIM)
• Low-voltage detection level select register (LVIS)
• Internal RAM data status register (RAMS)
(1) Low-voltage detection register (LVIM)
The LVIM register is a special register. This can be written only in the special combination of the sequences (see
3.4.7 Special registers).
The LVIM register is used to enable or disable low-voltage detection, and to set the operation mode of the low-
voltage detector.
This register can be read or written in 8-bit or 1-bit units. However, the LVIF bit is read-only.
After reset: Note 1 R/W Address: FFFFF890H
<7> 6 5 4 3 2 <1> <0>
LVIM LVION 0 0 0 0 0 LVIMD LVIF
LVION Low-voltage detection operation enable or disable
0 Disable operation.
1 Enable operation.
LVIMD Selection of operation mode of low-voltage detection
0
Generates interrupt request signal INTLVI when the supply voltage drops or rises
across the detection voltage value.
1
Generate internal reset signal LVIRES when the supply voltage drops across the
detected voltage value.
LV IF
Note 2
Low-voltage detection flag
0 When supply voltage > detected voltage, or when operation is disabled
1 Supply voltage of connected power supply < detected voltage
Notes 1. Reset by low-voltage detection: 82H
Reset due to other source: 00H
2. After the LVI operation has started (LVION bit = 1) or when INTLVI has occurred, confirm
the supply voltage state using the LVIF bit.
Cautions 1. When the LVION and LVIMD bits to 1, the low-voltage detector cannot be stopped
until the reset request due to other than the low-voltage detection is generated.
2. When the LVION bit is set to 1, the comparator in the LVI circuit starts operating.
Wait 0.2 ms or longer by software before checking the voltage at the LVIF bit after
the LVION bit is set.
3. Be sure to clear bits 6 to 2 to “0”.