Datasheet

V850ES/JG3 CHAPTER 23 CLOCK MONITOR
R01UH0015EJ0300 Rev.3.00 Page 706 of 870
Sep 30, 2010
(3) Operation in STOP mode or after STOP mode is released
If the STOP mode is set with the CLM.CLME bit = 1, the monitor operation is stopped in the STOP mode and while
the oscillation stabilization time is being counted. After the oscillation stabilization time, the monitor operation is
automatically started.
Figure 23-4. Operation in STOP Mode or After STOP Mode Is Released
Clock monitor
status
During
monitor
Monitor stops During monitor
CLME
Internal oscillation
clock
Main clock
CPU
operation
Normal
operation
STOP Oscillation stabilization time Normal operation
Oscillation stops
Oscillation stabilization time
(set by OSTS register)
(4) Operation when main clock is stopped (arbitrary)
During subclock operation (PCC.CLS bit = 1) or when the main clock is stopped by setting the PCC.MCK bit to 1,
the monitor operation is stopped until the main clock operation is started (PCC.CLS bit = 0). The monitor operation
is automatically started when the main clock operation is started.
Figure 23-5. Operation When Main Clock Is Stopped (Arbitrary)
Clock monitor
status
During
monitor
Monitor stops Monitor stops During monitor
CLME
Internal oscillation
clock
Main clock
CPU
operation
Oscillation stops
Subclock operation Main clock operation
Oscillation stabilization time
(set by OSTS register)
Oscillation stabilization
time count by software
PCC.MCK bit = 1
(5) Operation while CPU is operating on internal oscillation clock (CCLS.CCLSF bit = 1)
The monitor operation is not stopped when the CCLSF bit is 1, even if the CLME bit is set to 1.