Datasheet

V850ES/JG3 CHAPTER 23 CLOCK MONITOR
R01UH0015EJ0300 Rev.3.00 Page 704 of 870
Sep 30, 2010
23.4 Operation
This section explains the functions of the clock monitor. The start and stop conditions are as follows.
<Start condition>
Enabling operation by setting the CLM.CLME bit to 1
<Stop conditions>
• While oscillation stabilization time is being counted after STOP mode is released
• When the main clock is stopped (from when PCC.MCK bit = 1 during subclock operation to when PCC.CLS bit =
0 during main clock operation)
• When the sampling clock (internal oscillation clock) is stopped
• When the CPU operates using the internal oscillation clock
Table 23-2. Operation Status of Clock Monitor
(When CLM.CLME Bit = 1, During Internal Oscillation Clock Operation)
CPU Operating Clock Operation Mode Status of Main Clock
Status of Internal
Oscillation Clock
Status of Clock Monitor
HALT mode Oscillates Oscillates
Note 1
Operates
Note 2
IDLE1, IDLE2 modes Oscillates Oscillates
Note 1
Operates
Note 2
Main clock
STOP mode Stops Oscillates
Note 1
Stops
Subclock (MCK bit of
PCC register = 0)
Sub-IDLE mode Oscillates Oscillates
Note 1
Operates
Note 2
Subclock (MCK bit of
PCC register = 1)
Sub-IDLE mode Stops Oscillates
Note 1
Stops
Internal oscillation clock – Stops Oscillates
Note 3
Stops
During reset – Stops Stops Stops
Notes 1. The internal oscillator can be stopped by setting the RCM.RSTOP bit to 1.
2. The clock monitor is stopped while the internal oscillator is stopped.
3. The internal oscillator cannot be stopped by software.