Datasheet

V850ES/JG3 CHAPTER 23 CLOCK MONITOR
R01UH0015EJ0300 Rev.3.00 Page 703 of 870
Sep 30, 2010
23.3 Register
The clock monitor is controlled by the clock monitor mode register (CLM).
(1) Clock monitor mode register (CLM)
The CLM register is a special register. This can be written only in a special combination of sequences (see 3.4.7
Special registers).
This register is used to set the operation mode of the clock monitor.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H R/W Address: FFFFF870H
7 6 5 4 3 2 1 <0>
CLM 0 0 0 0 0 0 0 CLME
CLME Clock monitor operation enable or disable
0 Disable clock monitor operation.
1 Enable clock monitor operation.
Cautions 1. Once the CLME bit has been set to 1, it cannot be cleared to 0 by any means other
than reset.
2. When a reset by the clock monitor occurs, the CLME bit is cleared to 0 and the
RESF.CLMRF bit is set to 1.