Datasheet

V850ES/JG3 CHAPTER 23 CLOCK MONITOR
R01UH0015EJ0300 Rev.3.00 Page 702 of 870
Sep 30, 2010
CHAPTER 23 CLOCK MONITOR
23.1 Functions
The clock monitor samples the main clock by using the internal oscillation clock and generates a reset request signal
when oscillation of the main clock is stopped.
Once the operation of the clock monitor has been enabled by an operation enable flag, it cannot be cleared to 0 by any
means other than reset.
When a reset by the clock monitor occurs, the RESF.CLMRF bit is set. For details on the RESF register, see 22.2
Registers to Check Reset Source.
The clock monitor automatically stops under the following conditions.
• During oscillation stabilization time after STOP mode is released
• When the main clock is stopped (from when the PCC.MCK bit = 1 during subclock operation, until the PCC.CLS bit =
0 during main clock operation)
• When the sampling clock (internal oscillation clock) is stopped
• When the CPU operates with the internal oscillation clock
23.2 Configuration
The clock monitor includes the following hardware.
Table 23-1. Configuration of Clock Monitor
Item Configuration
Control register Clock monitor mode register (CLM)
Figure 23-1. Timing of Reset via the RESET Pin Input
Main clock
Internal oscillation
clock
Internal reset signal
Enable/disable
CLME
Clock monitor mode
register (CLM)