Datasheet

V850ES/JG3 CHAPTER 22 RESET FUNCTIONS
R01UH0015EJ0300 Rev.3.00 Page 700 of 870
Sep 30, 2010
22.3.4 Operation after reset release
After the reset is released, the main clock starts oscillation and oscillation stabilization time (OSTS register initial value:
2
16
/fX) is secured, and the CPU starts program execution.
WDT2 immediately begins to operate after a reset has been released using the internal oscillation clock as a source
clock.
Figure 22-5. Operation After Reset Release
Main clock
Reset
Counting of oscillation stabilization time Normal operation (f
CPU = Main clock)
Operation
stops
Operation in progress
Operation stops Operation in progress
Clock monitor
Internal oscillation
clock
V850ES/JG3
WDT2
(1) Emergent operation mode
If an anomaly occurs in the main clock before oscillation stabilization time is secured, WDT2 overflows before
executing the CPU program. At this time, the CPU starts program execution by using the internal oscillation clock
as the source clock.
Figure 22-6. Operation After Reset Release
Main clock
Reset Counting of oscillation stabilization time
WDT overflows
Emergency mode
(f
CPU = internal oscillation clock)
Operation
stops
Operation in progress Operation in progress (re-count)
Operation stops
Clock monitor
Internal oscillation
clock
V850ES/JG3
WDT2
The CPU operation clock states can be checked with the CPU operation clock status register (CCLS).