Datasheet

V850ES/JG3 CHAPTER 22 RESET FUNCTIONS
R01UH0015EJ0300 Rev.3.00 Page 699 of 870
Sep 30, 2010
22.3.3 Reset operation by low-voltage detector
If the supply voltage falls below the voltage detected by the low-voltage detector when LVI operation is enabled, a
system reset is executed (when the LVIM.LVIMD bit is set to 1), and the hardware is initialized to the initial status.
The reset status lasts from when a supply voltage drop has been detected until the supply voltage rises above the LVI
detection voltage.
The main clock oscillator is stopped during the reset period.
When the LVIMD bit = 0, an interrupt request signal (INTLVI) is generated if a low voltage is detected.
Table 22-3. Hardware Status During Reset Operation by Low-Voltage Detector
Item During Reset After Reset
Main clock oscillator (fX) Oscillation stops Oscillation starts
Subclock oscillator (fXT) Oscillation continues
Internal oscillator Oscillation stops Oscillation starts
Peripheral clock (fX to fX/1,024) Operation stops Operation starts after securing oscillation
stabilization time
Internal system clock (fXX),
CPU clock (f
CPU)
Operation stops Operation starts after securing oscillation
stabilization time (initialized to fXX/8)
CPU Initialized Program execution starts after securing
oscillation stabilization time
WDT2 Operation stops (initialized to 0) Counts up from 0 with internal oscillation
clock as source clock.
Internal RAM Undefined if power-on reset or CPU access and reset input conflict (data is damaged).
Otherwise value immediately after reset input is retained.
I/O lines (ports/alternate-function
pins)
High impedance
On-chip peripheral I/O register Initialized to specified status, OCDM register retains its value.
LVI Operation continues
On-chip peripheral functions other
than above
Operation stops Operation can be started after securing
oscillation stabilization time.
Remark For the reset timing of the low-voltage detector, see CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI).