Datasheet

V850ES/JG3 CHAPTER 22 RESET FUNCTIONS
R01UH0015EJ0300 Rev.3.00 Page 697 of 870
Sep 30, 2010
22.3.2 Reset operation by watchdog timer 2
When watchdog timer 2 is set to the reset operation mode due to overflow, upon watchdog timer 2 overflow (WDT2RES
signal generation), a system reset is executed and the hardware is initialized to the initial status.
Following watchdog timer 2 overflow, the reset status is entered and lasts the predetermined time (analog delay), and
the reset status is then automatically released.
The main clock oscillator is stopped during the reset period.
Table 22-2. Hardware Status During Watchdog Timer 2 Reset Operation
Item During Reset After Reset
Main clock oscillator (fX) Oscillation stops Oscillation starts
Subclock oscillator (fXT) Oscillation continues
Internal oscillator Oscillation stops Oscillation starts
Peripheral clock (fXX to fXX/1,024) Operation stops Operation starts after securing oscillation
stabilization time
Internal system clock (fXX),
CPU clock (f
CPU)
Operation stops Operation starts after securing oscillation
stabilization time (initialized to fXX/8)
CPU Initialized Program execution after securing
oscillation stabilization time
Watchdog timer 2 Operation stops (initialized to 0) Counts up from 0 with internal oscillation
clock as source clock.
Internal RAM Undefined if power-on reset or CPU access and reset input conflict (data is damaged).
Otherwise value immediately after reset input is retained.
I/O lines (ports/alternate-function
pins)
High impedance
On-chip peripheral I/O register Initialized to specified status, OCDM register retains its value.
On-chip peripheral functions other
than above
Operation stops Operation can be started after securing
oscillation stabilization time.