Datasheet

V850ES/JG3 CHAPTER 22 RESET FUNCTIONS
R01UH0015EJ0300 Rev.3.00 Page 696 of 870
Sep 30, 2010
Figure 22-2. Timing of Reset Operation by RESET Pin Input
Counting of oscillation
stabilization time
Initialized to f
XX /8 operation
Oscillation stabilization timer overflows
Internal system
reset signal
Analog delay
(eliminated as noise)
Analog delayAnalog delay
(eliminated as noise)
RESET
f
X
f CLK
Analog delay
Figure 22-3. Timing of Power-on Reset Operation
Oscillation stabilization
time count
Must be on-chip
regulator stabilization
time (1 ms (max.))
or longer.
Initialized to f
XX /8 operation
Overflow of timer for oscillation stabilization
Internal system
reset signal
RESET
f
X
V DD
f CLK
Analog delay