Datasheet

V850ES/JG3 CHAPTER 22 RESET FUNCTIONS
R01UH0015EJ0300 Rev.3.00 Page 693 of 870
Sep 30, 2010
CHAPTER 22 RESET FUNCTIONS
22.1 Overview
The following reset functions are available.
(1) Four kinds of reset sources
• External reset input via the RESET pin
• Reset via the watchdog timer 2 (WDT2) overflow (WDT2RES)
• System reset via the comparison of the low-voltage detector (LVI) supply voltage and detected voltage
• System reset via the detecting clock monitor (CLM) oscillation stop
After a reset is released, the source of the reset can be confirmed with the reset source flag register (RESF).
(2) Emergency operation mode
If the WDT2 overflows during the main clock oscillation stabilization time inserted after reset, a main clock
oscillation anomaly is judged and the CPU starts operating on the internal oscillation clock.
Caution In emergency operation mode, do not access on-chip peripheral I/O registers other than registers
used for interrupts, port function, WDT2, or timer M, each of which can operate with the internal
oscillation clock. In addition, operation of CSIB0 to CSIB4 and UARTA0 using the externally
input clock is also prohibited in this mode.
Figure 22-1. Block Diagram of Reset Function
CLMRF LVIRFWDT2RF
Reset source flag
register (RESF)
Internal bus
WDT2 reset signal
CLM reset signal
RESET
LVI reset signal
Reset signal
Reset signal
Reset signal to
LVIM/LVIS register
Clear
SetSet
Clear Clear
Set
Caution An LVI circuit internal reset does not reset the LVI circuit.
Remarks 1. LVIM: Low-voltage detection register
2. LVIS: Low-voltage detection level selection register