Datasheet

V850ES/JG3 CHAPTER 21 STANDBY FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 692 of 870
Sep 30, 2010
Table 21-11. Operation After Releasing Sub-IDLE Mode by Interrupt Request Signal
Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status
Non-maskable interrupt request
signal
Execution branches to the handler address.
Maskable interrupt request signal Execution branches to the handler address
or the next instruction is executed.
The next instruction is executed.
(2) Releasing sub-IDLE mode by reset
The same operation as the normal reset operation is performed.
Table 21-12. Operating Status in Sub-IDLE Mode
Setting of Sub-IDLE Mode Operating Status
Item When Main Clock Is Oscillating When Main Clock Is Stopped
Subclock oscillator Oscillation enabled
Internal oscillator Oscillation enabled
PLL Operable Stops operation
Note 1
CPU Stops operation
DMA Stops operation
Interrupt controller Stops operation (but standby mode release is possible)
Timer P (TMP0 to TMP5) Stops operation
Timer Q (TMQ0) Stops operation
Timer M (TMM0) Operable when fR/8 or fXT is selected as the count clock
Watch timer Stops operation Operable when fXT is selected as the
count clock
Watchdog timer 2 Operable when fR or fXT is selected as the count clock
CSIB0 to CSIB4 Operable when the SCKBn input clock is selected as the count clock (n = 0 to 4)
I
2
C00 to I
2
C02 Stops operation
Serial interface
UARTA0 to UARTA2 Stops operation (but UARTA0 is operable when the ASCKA0 input clock is selected)
A/D converter Holds operation (conversion result held)
Note 2
D/A converter Holds operation (output held
Note 2
)
Real-time output function (RTO) Stops operation (output held)
Key interrupt function (KR) Operable
CRC operation circuit Stops operation
External bus interface See 2.2 Pin States (same operation status as IDLE1, IDLE2 mode).
Port function Retains status before sub-IDLE mode was set
Internal data The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the sub-IDLE mode was set.
Notes 1. Be sure to stop the PLL (PLLCTL.PLLON bit = 0) before stopping the main clock.
2. To realize low power consumption, stop the A/D and D/A converters before shifting to the sub-IDLE mode.