Datasheet

V850ES/JG3 CHAPTER 21 STANDBY FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 691 of 870
Sep 30, 2010
21.8 Sub-IDLE Mode
21.8.1 Setting and operation status
The sub-IDLE mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 00 or 10 and setting the PSC.STP bit to
1 in the subclock operation mode.
In this mode, the clock oscillator continues operating but clock supply to the CPU, flash memory, and the other on-chip
peripheral functions is stopped.
As a result, program execution stops and the contents of the internal RAM before the sub-IDLE mode was set are
retained. The CPU and the other on-chip peripheral functions are stopped. However, the on-chip peripheral functions that
can operate with the subclock or an external clock continue operating.
Because the sub-IDLE mode stops operation of the CPU, flash memory, and other on-chip peripheral functions, it can
reduce the power consumption more than the subclock operation mode. If the sub-IDLE mode is set after the main clock
has been stopped, the current consumption can be reduced to a level as low as that in the STOP mode.
Table 21-12 shows the operating status in the sub-IDLE mode.
Cautions 1. Following the store instruction to the PSC register for setting the sub-IDLE mode, insert the five
or more NOP instructions.
2. If the sub-IDLE mode is set while an unmasked interrupt request signal is being held pending, the
sub-IDLE mode is then released immediately by the pending interrupt request.
21.8.2 Releasing sub-IDLE mode
The sub-IDLE mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal),
unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt request signal from the
peripheral functions operable in the sub-IDLE mode, or reset signal (reset by RESET pin input, WDT2RES signal, low-
voltage detector (LVI), or clock monitor (CLM)). The PLL returns to the operating status it was in before the sub-IDLE
mode was set.
When the sub-IDLE mode is released by an interrupt request signal, the subclock operation mode is set.
(1) Releasing sub-IDLE mode by non-maskable interrupt request signal or unmasked maskable interrupt
request signal
The sub-IDLE mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt
request signal, regardless of the priority of the interrupt request signal.
If the sub-IDLE mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later
is serviced as follows.
(a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is
issued, the sub-IDLE mode is released, but that interrupt request signal is not acknowledged. The interrupt
request signal itself is retained.
(b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is
issued (including a non-maskable interrupt request signal), the sub-IDLE mode is released and that interrupt
request signal is acknowledged.
Cautions 1. The interrupt request signal that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and
PSC.INTM bits to 1 becomes invalid and sub-IDLE mode is not released.
2. When the sub-IDLE mode is released, 12 cycles of the subclock (about 366
μ s) elapse from
when the interrupt request signal that releases the sub-IDLE mode is generated to when the
mode is released.