Datasheet

V850ES/JG3 CHAPTER 21 STANDBY FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 690 of 870
Sep 30, 2010
Table 21-10. Operating Status in Subclock Operation Mode
Operating Status Setting of Subclock Operation Mode
Item
When Main Clock Is Oscillating When Main Clock Is Stopped
Subclock oscillator Oscillation enabled
Internal oscillator Oscillation enabled
PLL Operable Stops operation
Note
CPU Operable
DMA Operable
Interrupt controller Operable
Timer P (TMP0 to TMP5) Operable Stops operation
Timer Q (TMQ0) Operable Stops operation
Timer M (TMM0) Operable Operable when fR/8 or fXT is selected as
the count clock
Watch timer Operable Operable when fXT is selected as the
count clock
Watchdog timer 2 Operable Operable when fR or fXT is selected as
the count clock
CSIB0 to CSIB4 Operable Operable when the SCKBn input clock is
selected as the count clock (n = 0 to 4)
I
2
C00 to I
2
C02 Operable Stops operation
Serial interface
UARTA0 to UARTA2 Operable Stops operation (but UARTA0 is
operable when the ASCKA0 input clock
is selected)
A/D converter Operable Stops operation
D/A converter Operable
Real-time output function (RTO) Operable Stops operation (output held)
Key interrupt function (KR) Operable
CRC operation circuit Operable
External bus interface See 2.2 Pin States.
Port function Settable
Internal data Settable
Note Be sure to stop the PLL (PLLCTL.PLLON bit = 0) before stopping the main clock.
Caution When the CPU is operating on the subclock and main clock oscillation is stopped, accessing a
register in which a wait occurs is disabled. If a wait is generated, it can be released only by reset
(see 3.4.8 (2)).