Datasheet

V850ES/JG3 CHAPTER 21 STANDBY FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 687 of 870
Sep 30, 2010
(2) Releasing STOP mode by reset
The same operation as the normal reset operation is performed.
Table 21-9. Operating Status in STOP Mode
Setting of STOP Mode Operating Status
Item When Subclock Is Not Used When Subclock Is Used
Main clock oscillator Stops oscillation
Subclock oscillator
−
Oscillation enabled
Internal oscillator Oscillation enabled
PLL Stops operation
CPU Stops operation
DMA Stops operation
Interrupt controller Stops operation (but standby mode release is possible)
Timer P (TMP0 to TMP5) Stops operation
Timer Q (TMQ0) Stops operation
Timer M (TMM0) Operable when fR/8 is selected as the
count clock
Operable when fR/8 or fXT is selected as
the count clock
Watch timer Stops operation Operable when fXT is selected as the
count clock
Watchdog timer 2 Operable when fR is selected as the
count clock
Operable when fR or fXT is selected as
the count clock
CSIB0 to CSIB4 Operable when the SCKBn input clock is selected as the count clock (n = 0 to 4)
I
2
C00 to I
2
C02 Stops operation
Serial interface
UARTA0 to UARTA2 Stops operation (but UARTA0 is operable when the ASCKA0 input clock is selected)
A/D converter Stops operation (conversion result undefined)
Notes 1, 2
D/A converter Stops operation
Notes 3, 4
(high impedance is output)
Real-time output function (RTO) Stops operation (output held)
Key interrupt function (KR) Operable
CRC operation circuit Stops operation
External bus interface See 2.2 Pin States.
Port function Retains status before STOP mode was set
Internal data The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the STOP mode was set.
Notes 1. If the STOP mode is set while the A/D converter is operating, the A/D converter is automatically stopped and
starts operating again after the STOP mode is released. However, in that case, the A/D conversion results
after the STOP mode is released are invalid. All the A/D conversion results before the STOP mode is set are
invalid.
2. Even if the STOP mode is set while the A/D converter is operating, the power consumption is reduced
equivalently to when the A/D converter is stopped before the STOP mode is set.
3. If the STOP mode is set while the D/A converter is operating, the D/A converter is automatically stopped and
the pin status becomes high impedance. After the STOP mode is released, D/A conversion resumes, the
setting time elapses, and the status returns to the output level before the STOP mode was set.
4. Even if the STOP mode is set while the D/A converter is operating, the power consumption is reduced
equivalently to when the D/A converter is stopped before the STOP mode is set.