Datasheet

V850ES/JG3 CHAPTER 21 STANDBY FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 684 of 870
Sep 30, 2010
21.5.3 Securing setup time when releasing IDLE2 mode
Secure the setup time for the flash memory after releasing the IDLE2 mode because the operation of the blocks other
than the main clock oscillator stops after the IDLE2 mode is set.
(1) Releasing IDLE2 mode by non-maskable interrupt request signal or unmasked maskable interrupt request
signal
Secure the specified setup time by setting the OSTS register.
When the releasing source is generated, the dedicated internal timer starts counting according to the OSTS
register setting. When it overflows, the normal operation mode is restored.
Oscillated waveform
ROM circuit stopped Setup time count
Main clock
IDLE mode status
Interrupt request
(2) Release by reset (RESET pin input, WDT2RES generation)
This operation is the same as that of a normal reset.
The oscillation stabilization time is the initial value of the OSTS register, 2
16
/fX.