Datasheet

V850ES/JG3 CHAPTER 3 CPU FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 54 of 870
Sep 30, 2010
(8/10)
Manipulatable Bits Address Function Register Name Symbol R/W
1 8 16
Default Value
FFFFF812H DMA trigger factor register 1 DTFR1
√ √
00H
FFFFF814H DMA trigger factor register 2 DTFR2
√ √
00H
FFFFF816H DMA trigger factor register 3 DTFR3
√ √
00H
FFFFF820H Power save mode register PSMR
√ √
00H
FFFFF822H Clock control register CKC
R/W
√ √
0AH
FFFFF824H Lock register LOCKR R
√ √
00H
FFFFF828H Processor clock control register PCC
√ √
03H
FFFFF82CH PLL control register PLLCTL
R/W
√ √
01H
FFFFF82EH CPU operation clock status register CCLS
√ √
00H
FFFFF870H Clock monitor mode register CLM
√ √
00H
FFFFF888H Reset source flag register RESF
√ √
00H
FFFFF890H Low-voltage detection register LVIM
√ √
00H
FFFFF891H Low-voltage detection level select register LVIS
√
00H
FFFFF892H Internal RAM data status register RAMS
√ √
01H
FFFFF8B0H Prescaler mode register 0 PRSM0
√ √
00H
FFFFF8B1H Prescaler compare register 0 PRSCM0
√
00H
FFFFF9FCH On-chip debug mode register OCDM
√ √
01H
FFFFF9FEH Peripheral emulation register 1 PEMU1
Note
√ √
00H
FFFFFA00H UARTA0 control register 0 UA0CTL0
√ √
10H
FFFFFA01H UARTA0 control register 1 UA0CTL1
√
00H
FFFFFA02H UARTA0 control register 2 UA0CTL2
√
FFH
FFFFFA03H UARTA0 option control register 0 UA0OPT0
√ √
14H
FFFFFA04H UARTA0 status register UA0STR
√ √
00H
FFFFFA06H UARTA0 receive data register UA0RX
R
√
FFH
FFFFFA07H UARTA0 transmit data register UA0TX
√
FFH
FFFFFA10H UARTA1 control register 0 UA1CTL0
√ √
10H
FFFFFA11H UARTA1 control register 1 UA1CTL1
√
00H
FFFFFA12H UARTA1 control register 2 UA1CTL2
√
FFH
FFFFFA13H UARTA1 option control register 0 UA1OPT0
√ √
14H
FFFFFA14H UARTA1 status register UA1STR
R/W
√ √
00H
FFFFFA16H UARTA1 receive data register UA1RX R
√
FFH
FFFFFA17H UARTA1 transmit data register UA1TX
√
FFH
FFFFFA20H UARTA2 control register 0 UA2CTL0
√ √
10H
FFFFFA21H UARTA2 control register 1 UA2CTL1
√
00H
FFFFFA22H UARTA2 control register 2 UA2CTL2
√
FFH
FFFFFA23H UARTA2 option control register 0 UA2OPT0
√ √
14H
FFFFFA24H UARTA2 status register UA2STR
R/W
√ √
00H
FFFFFA26H UARTA2 receive data register UA2RX R
√
FFH
FFFFFA27H UARTA2 transmit data register UA2TX
√
FFH
FFFFFC00H External interrupt falling edge specification register 0 INTF0
√ √
00H
FFFFFC06H External interrupt falling edge specification register 3 INTF3
R/W
√ √
00H
Note Only during emulation