Datasheet

V850ES/JG3 CHAPTER 21 STANDBY FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 679 of 870
Sep 30, 2010
(2) Releasing HALT mode by reset
The same operation as the normal reset operation is performed.
Table 21-3. Operating Status in HALT Mode
Setting of HALT Mode Operating Status
Item When Subclock Is Not Used When Subclock Is Used
Main clock oscillator Oscillation enabled
Subclock oscillator
−
Oscillation enabled
Internal oscillator Oscillation enabled
PLL Operable
CPU Stops operation
DMA Operable
Interrupt controller Operable
Timer P (TMP0 to TMP5) Operable
Timer Q (TMQ0) Operable
Timer M (TMM0) Operable when a clock other than fXT is
selected as the count clock
Operable
Watch timer Operable when fX (divided BRG) is
selected as the count clock
Operable
Watchdog timer 2 Operable when a clock other than fXT is
selected as the count clock
Operable
CSIB0 to CSIB4 Operable
I
2
C00 to I
2
C02 Operable
Serial interface
UARTA0 to UARTA2 Operable
A/D converter Operable
D/A converter Operable
Real-time output function (RTO) Operable
Key interrupt function (KR) Operable
CRC operation circuit Operable (No data input to the CRCIN register because the CPU is stopped)
External bus interface See 2.2 Pin States.
Port function Retains status before HALT mode was set
Internal data The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the HALT mode was set.