Datasheet

V850ES/JG3 CHAPTER 21 STANDBY FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 678 of 870
Sep 30, 2010
21.3 HALT Mode
21.3.1 Setting and operation status
The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode.
In the HALT mode, the clock oscillator continues operating. Only clock supply to the CPU is stopped; clock supply to
the other on-chip peripheral functions continues.
As a result, program execution is stopped, and the internal RAM retains the contents before the HALT mode was set.
The on-chip peripheral functions that are independent of instruction processing by the CPU continue operating.
Table 21-3 shows the operating status in the HALT mode.
The average current consumption of the system can be reduced by using the HALT mode in combination with the
normal operation mode for intermittent operation.
Cautions 1. Insert five or more NOP instructions after the HALT instruction.
2. If the HALT instruction is executed while an unmasked interrupt request signal is being held
pending, the status shifts to HALT mode, but the HALT mode is then released immediately by the
pending interrupt request.
21.3.2 Releasing HALT mode
The HALT mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked
external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt request signal from a peripheral
function operable in the HALT mode, or reset signal (reset by RESET pin input, WDT2RES signal, low-voltage detector
(LVI), or clock monitor (CLM)).
After the HALT mode has been released, the normal operation mode is restored.
(1) Releasing HALT mode by non-maskable interrupt request signal or unmasked maskable interrupt request
signal
The HALT mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt
request signal, regardless of the priority of the interrupt request signal. If the HALT mode is set in an interrupt
servicing routine, however, an interrupt request signal that is issued later is serviced as follows.
(a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is
issued, the HALT mode is released, but that interrupt request signal is not acknowledged. The interrupt
request signal itself is retained.
(b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is
issued (including a non-maskable interrupt request signal), the HALT mode is released and that interrupt
request signal is acknowledged.
Table 21-2. Operation After Releasing HALT Mode by Interrupt Request Signal
Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status
Non-maskable interrupt request
signal
Execution branches to the handler address.
Maskable interrupt request signal Execution branches to the handler address
or the next instruction is executed.
The next instruction is executed.