Datasheet

V850ES/JG3 CHAPTER 21 STANDBY FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 677 of 870
Sep 30, 2010
(3) Oscillation stabilization time select register (OSTS)
The wait time until the oscillation stabilizes after the STOP mode is released or the wait time until the on-chip flash
memory stabilizes after the IDLE2 mode is released is controlled by the OSTS register.
The OSTS register can be read or written 8-bit units.
Reset sets this register to 06H.
0OSTS 0 0 0 0 OSTS2 OSTS1 OSTS0
OSTS2
0
0
0
0
1
1
1
1
Selection of oscillation stabilization time/setup time
Note
OSTS1
0
0
1
1
0
0
1
1
OSTS0
0
1
0
1
0
1
0
1
After reset: 06H R/W Address: FFFFF6C0H
2
10
/fX
2
11
/fX
2
12
/fX
2
13
/fX
2
14
/fX
2
15
/fX
2
16
/fX
4 MHz
0.256 ms
0.512 ms
1.024 ms
2.048 ms
4.096 ms
8.192 ms
16.38 ms
5 MHz
0.205 ms
0.410 ms
0.819 ms
1.638 ms
3.277 ms
6.554 ms
13.107 ms
f
X
Setting prohibited
Note The oscillation stabilization time and setup time are required when the STOP mode and
IDLE2 mode are released, respectively.
Cautions 1. The wait time following release of the STOP mode does not include the time
until the clock oscillation starts (“a” in the figure below) following release of
the STOP mode, regardless of whether the STOP mode is released by reset or
the occurrence of an interrupt request signal.
a
STOP mode release
Voltage waveform of X1 pin
V
SS
2. Be sure to clear bits 3 to 7 to “0”.
3. The oscillation stabilization time following reset release is 2
16
/fX (because the
initial value of the OSTS register = 06H).
Remark f
X = Main clock oscillation frequency