Datasheet

V850ES/JG3 CHAPTER 21 STANDBY FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 675 of 870
Sep 30, 2010
21.2 Registers
(1) Power save control register (PSC)
The PSC register is an 8-bit register that controls the standby function. The STP bit of this register is used to
specify the STOP mode. This register is a special register that can be written only by the special sequence
combinations (see 3.4.7 Special registers).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
0PSC NMI1M NMI0M INTM 0 0 STP 0
Releasing standby mode by INTWDT2 signal enabled
Releasing standby mode by INTWDT2 signal disabled
NMI1M
0
1
Control of releasing standby mode by INTWDT2 signal
Releasing standby mode by NMI pin input enabled
Releasing standby mode by NMI pin input disabled
NMI0M
0
1
Control of releasing standby mode by NMI pin input
Releasing standby mode by maskable interrupt request signals enabled
Releasing standby mode by maskable interrupt request signals disabled
INTM
0
1
Control of releasing standby mode by maskable interrupt request signals
Normal mode
Standby mode
STP
0
1
Standby mode setting
After reset: 00H R/W Address: FFFFF1FEH
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Note Standby mode set by STP bit: IDLE1, IDLE2, STOP, or sub-IDLE mode
Cautions 1. Before setting the IDLE1, IDLE2, STOP, or sub-IDLE mode, set the PSMR.PSM1
and PSMR.PSM0 bits and then set the STP bit.
2. Settings of the NMI1M, NMI0M, and INTM bits are invalid when HALT mode is
released.
3. If the NMI1M, NMI0M, or INTM bit is set to 1 at the same time the STP bit is set
to 1, the setting of NMI1M, NMI0M, or INTM bit becomes invalid. If there is an
unmasked interrupt request signal being held pending when the
IDLE1/IDLE2/STOP mode is set, set the bit corresponding to the interrupt
request signal (NMI1M, NMI0M, or INTM) to 1, and then set the STP bit to 1.