Datasheet

V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 669 of 870
Sep 30, 2010
19.7 Interrupt Acknowledge Time of CPU
Except the following cases, the interrupt acknowledge time of the CPU is 4 clocks minimum. To input interrupt request
signals successively, input the next interrupt request signal at least 5 clocks after the preceding interrupt.
• In IDLE1/IDLE2/STOP mode
• When the external bus is accessed
• When interrupt request non-sampling instructions are successively executed (see 19.8 Periods in Which Interrupts
Are Not Acknowledged by CPU.)
• When the interrupt control register is accessed
Figure 19-15. Pipeline Operation at Interrupt Request Signal Acknowledgment (Outline)
(1) Minimum interrupt response time
IF ID EX
Internal clock
Instruction 1
Instruction 2
Interrupt acknowledgment operation
Instruction (first instruction of interrupt servicing routine)
Interrupt request
IF ID EX
MEM WB
IFX IDX
INT1 INT2 INT3 INT4
4 system clocks
(2) Maximum interrupt response time
IF ID EX
Internal clock
Instruction 1
Instruction 2
Interrupt acknowledgment operation
Instruction (first instruction of interrupt servicing routine)
Interrupt request
IF ID EX
MEM MEM MEM WB
IFX IDX
INT1 INT2 INT3 INT3 INT3 INT4
6 system clocks
Remark INT1 to INT4: Interrupt acknowledgment processing
IFX: Invalid instruction fetch
IDX: Invalid instruction decode
Interrupt acknowledge time (internal system clock)
Internal interrupt External interrupt
Condition
Minimum 4 4 +
Analog delay time
Maximum 6 6 +
Analog delay time
The following cases are exceptions.
• In IDLE1/IDLE2/STOP mode
• External bus access
• Two or more interrupt request non-sample instructions are
executed in succession
• Access to peripheral I/O register