Datasheet

V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 668 of 870
Sep 30, 2010
(4) Noise elimination control register (NFC)
Digital noise elimination can be selected for the INTP3 pin. The noise elimination settings are performed using the
NFC register.
When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among
f
XX/64, fXX/128, fXX/256, fXX/512, fXX/1,024, and fXT. Sampling is performed three times.
When digital noise elimination is selected, if the clock that performs sampling in the standby mode is stopped, then
the INTP3 interrupt request signal cannot be used for releasing the standby mode. When f
XT is used as the
sampling clock, the INTP3 interrupt request signal can be used for releasing either the subclock operating mode or
the IDLE1/IDLE2/STOP/sub-IDLE mode.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Caution After the sampling clock has been changed, it takes 3 sampling clocks to initialize the digital
noise eliminator. Therefore, if an INTP3 valid edge is input within these 3 sampling clocks after
the sampling clock has been changed, an interrupt request signal may be generated. Therefore,
be careful about the following points when using the interrupt and DMA functions.
• When using the interrupt function, after the 3 sampling clocks have elapsed, enable interrupts
after the interrupt request flag (PIC3.PIF3 bit) has been cleared.
• When using the DMA function (started by INTP3), enable DMA after 3 sampling clocks have
elapsed.
NFENNFC 0 0 0 0 NFC2 NFC1 NFC0
fXX/64
f
XX/128
f
XX/256
f
XX/512
f
XX/1,024
f
XT (subclock)
NFC2
0
0
0
0
1
1
Digital sampling clock
Setting prohibited
NFC1
0
0
1
1
0
0
NFC0
0
1
0
1
0
1
After reset: 00H R/W Address: FFFFF318H
Analog noise elimination (60 ns (TYP.))
Digital noise elimination
NFEN
0
1
Settings of INTP3 pin noise elimination
Other than above
Remarks 1. Since sampling is performed three times, the reliably eliminated noise width is 2 sampling clocks.
2. In the case of noise with a width smaller than 2 sampling clocks, an interrupt request signal is
generated if noise synchronized with the sampling clock is input.