Datasheet

V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 665 of 870
Sep 30, 2010
(1) External interrupt falling, rising edge specification register 0 (INTF0, INTR0)
The INTF0 and INTR0 registers are 8-bit registers that specify detection of the falling and rising edges of the NMI
pin via bit 2 and the external interrupt pins (INTP0 to INTP3) via bits 3 to 6.
These registers can be read or written in 8-bit or 1-bit units.
Reset sets these registers to 00H.
Caution When the function is changed from the external interrupt function (alternate function) to the port
function, an edge may be detected. Therefore, clear the INTF0n and INTR0n bits to 00, and then
set the port mode.
0INTF0 INTF06
INTP3
INTF05 INTF04 INTF03 INTF02 0 0
After reset: 00H R/W Address: INTF0 FFFFFC00H, INTR0 FFFFFC20H
0INTR0 INTR06 INTR05 INTR04 INTR03 INTR02 0 0
INTP2 INTP1 INTP0 NMI
INTP3 INTP2 INTP1 INTP0 NMI
Remark For how to specify a valid edge, see Table 19-3.
Table 19-3. Valid Edge Specification
INTF0n INTR0n Valid Edge Specification (n = 2 to 6)
0 0 No edge detected
0 1 Rising edge
1 0 Falling edge
1 1 Both rising and falling edges
Caution Be sure to clear the INTF0n and INTR0n bits to 00 when these registers are not used as the NMI
or INTP0 to INTP3 pins.
Remark n = 2: Control of NMI pin
n = 3 to 6: Control of INTP0 to INTP3 pins