Datasheet

V850ES/JG3 CHAPTER 3 CPU FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 52 of 870
Sep 30, 2010
(6/10)
Manipulatable Bits Address Function Register Name Symbol R/W
1 8 16
Default Value
FFFFF484H Data wait control register 0 DWC0
√
7777H
FFFFF488H Address wait control register AWC
√
FFFFH
FFFFF48AH Bus cycle control register BCC
√
AAAAH
FFFFF540H TMQ0 control register 0 TQ0CTL0
√ √
00H
FFFFF541H TMQ0 control register 1 TQ0CTL1
√ √
00H
FFFFF542H TMQ0 I/O control register 0 TQ0IOC0
√ √
00H
FFFFF543H TMQ0 I/O control register 1 TQ0IOC1
√ √
00H
FFFFF544H TMQ0 I/O control register 2 TQ0IOC2
√ √
00H
FFFFF545H TMQ0 option register 0 TQ0OPT0
√ √
00H
FFFFF546H TMQ0 capture/compare register 0 TQ0CCR0
√
0000H
FFFFF548H TMQ0 capture/compare register 1 TQ0CCR1
√
0000H
FFFFF54AH TMQ0 capture/compare register 2 TQ0CCR2
√
0000H
FFFFF54CH TMQ0 capture/compare register 3 TQ0CCR3
R/W
√
0000H
FFFFF54EH TMQ0 counter read buffer register TQ0CNT R
√
0000H
FFFFF590H TMP0 control register 0 TP0CTL0
√ √
00H
FFFFF591H TMP0 control register 1 TP0CTL1
√ √
00H
FFFFF592H TMP0 I/O control register 0 TP0IOC0
√ √
00H
FFFFF593H TMP0 I/O control register 1 TP0IOC1
√ √
00H
FFFFF594H TMP0 I/O control register 2 TP0IOC2
√ √
00H
FFFFF595H TMP0 option register 0 TP0OPT0
√ √
00H
FFFFF596H TMP0 capture/compare register 0 TP0CCR0
√
0000H
FFFFF598H TMP0 capture/compare register 1 TP0CCR1
R/W
√
0000H
FFFFF59AH TMP0 counter read buffer register TP0CNT R
√
0000H
FFFFF5A0H TMP1 control register 0 TP1CTL0
√ √
00H
FFFFF5A1H TMP1 control register 1 TP1CTL1
√ √
00H
FFFFF5A2H TMP1 I/O control register 0 TP1IOC0
√ √
00H
FFFFF5A3H TMP1 I/O control register 1 TP1IOC1
√ √
00H
FFFFF5A4H TMP1 I/O control register 2 TP1IOC2
√ √
00H
FFFFF5A5H TMP1 option register 0 TP1OPT0
√ √
00H
FFFFF5A6H TMP1 capture/compare register 0 TP1CCR0
√
0000H
FFFFF5A8H TMP1 capture/compare register 1 TP1CCR1
R/W
√
0000H
FFFFF5AAH TMP1 counter read buffer register TP1CNT R
√
0000H
FFFFF5B0H TMP2 control register 0 TP2CTL0
√ √
00H
FFFFF5B1H TMP2 control register 1 TP2CTL1
√ √
00H
FFFFF5B2H TMP2 I/O control register 0 TP2IOC0
√ √
00H
FFFFF5B3H TMP2 I/O control register 1 TP2IOC1
√ √
00H
FFFFF5B4H TMP2 I/O control register 2 TP2IOC2
√ √
00H
FFFFF5B5H TMP2 option register 0 TP2OPT0
√ √
00H
FFFFF5B6H TMP2 capture/compare register 0 TP2CCR0
√
0000H
FFFFF5B8H TMP2 capture/compare register 1 TP2CCR1
R/W
√
0000H
FFFFF5BAH TMP2 counter read buffer register TP2CNT R
√
0000H
FFFFF5C0H TMP3 control register 0 TP3CTL0
√ √
00H
FFFFF5C1H TMP3 control register 1 TP3CTL1
R/W
√ √
00H