Datasheet

V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 660 of 870
Sep 30, 2010
19.5 Exception Trap
An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the
V850ES/JG3, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap.
19.5.1 Illegal opcode definition
The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 0111B to 1111B, and a
sub-opcode (bit 16) of 0B. An exception trap is generated when an instruction applicable to this illegal instruction is
executed.
15 1623 22
xxxxxx0xxxxxxxxxx111111xxxxx
27 26310451011
1
1
1
1
1
1
0
1
to
x: Arbitrary
Caution Since it is possible to assign this instruction to an illegal opcode in the future, it is recommended
that it not be used.
(1) Operation
If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler
routine.
<1> Saves the restored PC to DBPC.
<2> Saves the current PSW to DBPSW.
<3> Sets the PSW.NP, PSW.EP, and PSW.ID bits to 1.
<4> Sets the handler address (00000060H) corresponding to the exception trap to the PC, and transfers control.
The processing of the exception trap is shown below.
Figure 19-11. Exception Trap Processing
Exception trap (ILGOP) occurs
DBPC
DBPSW
PSW.NP
PSW.EP
PSW.ID
PC
Restored PC
PSW
1
1
1
00000060H
Exception processing
CPU processing