Datasheet

V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 656 of 870
Sep 30, 2010
19.3.7 ID flag
This flag controls the maskable interrupt’s operating state, and stores control information regarding enabling or
disabling of interrupt request signals. An interrupt disable flag (ID) is assigned to the PSW.
Reset sets this flag to 00000020H.
0
NP EP ID SAT CY OV S Z
PSW
Maskable interrupt request signal acknowledgment enabled
Maskable interrupt request signal acknowledgment disabled (pending)
ID
0
1
Specification of maskable interrupt servicing
Note
After reset: 00000020H
Note Interrupt disable flag (ID) function
This bit is set to 1 by the DI instruction and cleared to 0 by the EI instruction. Its value is also modified by
the RETI instruction or LDSR instruction when referencing the PSW.
Non-maskable interrupt request signals and exceptions are acknowledged regardless of this flag. When
a maskable interrupt request signal is acknowledged, the ID flag is automatically set to 1 by hardware.
The interrupt request signal generated during the acknowledgment disabled period (ID flag = 1) is
acknowledged when the xxICn.xxIFn bit is set to 1, and the ID flag is cleared to 0.
19.3.8 Watchdog timer mode register 2 (WDTM2)
This register can be read or written in 8-bit units (for details, see CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER
2).
Reset sets this register to 67H.
0WDTM2 WDM21 WDM20 0 0 0 0 0
After reset: 67H R/W Address: FFFFF6D0H
Stops operation
Non-maskable interrupt request mode
Reset mode (initial-value)
WDM21
0
0
1
WDM20
0
1
×
Selection of watchdog timer operation mode