Datasheet

V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 655 of 870
Sep 30, 2010
19.3.6 In-service priority register (ISPR)
The ISPR register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request
signal is acknowledged, the bit of this register corresponding to the priority level of that interrupt request signal is set to 1
and remains set while the interrupt is serviced.
When the RETI instruction is executed, the bit corresponding to the interrupt request signal having the highest priority is
automatically reset to 0 by hardware. However, it is not reset to 0 when execution is returned from non-maskable interrupt
servicing or exception processing.
This register is read-only, in 8-bit or 1-bit units.
Reset sets this register to 00H.
Caution If an interrupt is acknowledged while the ISPR register is being read in the interrupt enabled (EI)
status, the value of the ISPR register after the bits of the register have been set by acknowledging the
interrupt may be read. To accurately read the value of the ISPR register before an interrupt is
acknowledged, read the register while interrupts are disabled (DI).
ISPR7
Interrupt request signal with priority n not acknowledged
Interrupt request signal with priority n acknowledged
ISPRn
0
1
Priority of interrupt currently acknowledged
ISPR ISPR6 ISPR5 ISPR4 ISPR3 ISPR2 ISPR1 ISPR0
After reset: 00H R Address: FFFFF1FAH
<7> <6> <5> <4> <3> <2> <1> <0>
Remark n = 0 to 7 (priority level)