Datasheet

V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 654 of 870
Sep 30, 2010
TP0CCMK0
PMK6
IMR0 (IMR0H
Note
)
IMR0L
TP0OVMK
PMK5
TQ0CCMK3
PMK4
TQ0CCMK2
PMK3
TQ0CCMK1
PMK2
TQ0CCMK0
PMK1
TQ0OVMK
PMK0
PMK7
LVIMK
After reset: FFFFH R/W Address: IMR0 FFFFF100H,
IMR0L FFFFF100H, IMR0H FFFFF101H
After reset: FFFFH R/W Address: IMR1 FFFFF102H,
IMR1L FFFFF102H, IMR1H FFFFF103H
After reset: FFFFH R/W Address: IMR2 FFFFF104H,
IMR2L FFFFF104H, IMR2H FFFFF105H
TP5CCMK1
TP3OVMK
IMR1 (IMR1H
Note
)
IMR1L
TP5CCMK0
TP2CCMK1
TP5OVMK
TP2CCMK0
TP4CCMK1
TP2OVMK
TP4CCMK0
TP1CCMK1
TP4OVMK
TP1CCMK0
TP3CCMK1
TP1OVMK
TP3CCMK0
TP0CCMK1
ADMK
CB3RMK
CB3TMK
TM0EQMK0
xxMKn
0
1
Interrupt servicing enabled
Interrupt servicing disabled
IMR2 (IMR2H
Note
)
IMR2L
UA2TMK
CB2TMK CB2RMK
UA1TMK
CB1TMK CB1RMK CB0TMK
UA0TMK/
CB4TMK
UA2RMK/
IICMK0
UA0RMK/
CB4RMK
CB0RMK/
IICMK1
8
910
11
12131415
1234567 0
1IMR3 (IMR3H
Note
)
IMR3L
1
WTMK
1
WTIMK
1
KRMK
1
DMAMK3 DMAMK2 DMAMK1 DMAMK0
After reset: FFFFH R/W Address: IMR3 FFFFF106H,
IMR3L FFFFF106H, IMR3H FFFFF107H
8
1
9
1
10
1
11
12131415
1234567
1
0
8
910
11
12131415
1234567 0
8
910
11
1213
Setting of interrupt mask flag
1415
1234567 0
UA1RMK/
IIC2MK
Note To read bits 8 to 15 of the IMR0 to IMR3 registers in 8-bit or 1-bit units, specify them as bits 0 to 7 of
IMR0H to IMR3H registers.
Caution Set bits 7 to 15 of the IMR3 register to 1. If the setting of these bits is changed, the operation
is not guaranteed.
Remark xx: Identification name of each peripheral unit (see Table 19-2 Interrupt Control Register
(xxICn)).
n: Peripheral unit number (see Table 19-2 Interrupt Control Register (xxICn))