Datasheet

V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 653 of 870
Sep 30, 2010
Table 19-2. Interrupt Control Register (xxICn) (2/2)
Bit Address Register
<7> <6> 5 4 3 2 1 0
FFFFF162H UA0RIC/
CB4RIC
UA0RIF/
CB4RIF
UA0RMK/
CB4RMK
0 0 0 UA0RPR2/
CB4RPR2
UA0RPR1/
CB4RPR1
UA0RPR0/
CB4RPR0
FFFFF164H UA0TIC/
CB4TIC
UA0TIF/
CB4TIF
UA0TMK/
CB4TMK
0 0 0 UA0TPR2/
CB4TPR2
UA0TPR1/
CB4TPR1
UA0TPR0/
CB4TPR0
FFFFF166H UA1RIC/
IICIC2
UA1RIF/
IICIF2
UA1RMK/
IICMK2
0 0 0 UA1RPR2/
IICPR22
UA1RPR1/
IICPR21
UA1RPR0/
IICPR20
FFFFF168H UA1TIC UA1TIF UA1TMK 0 0 0 UA1TPR2 UA1TPR1 UA1TPR0
FFFFF16AH UA2RIC/
IICIC0
UA2RIF/
IICIF0
UA2RMK/
IICMK0
0 0 0 UA2RPR2/
IICPR02
UA2RPR1/
IICPR01
UA2RPR0/
IICPR00
FFFFF16CH UA2TIC UA2TIF UA2TMK 0 0 0 UA2TPR2 UA2TPR1 UA2TPR0
FFFFF16EH ADIC ADIF ADMK 0 0 0 ADPR2 ADPR1 ADPR0
FFFFF170H DMAIC0 DMAIF0 DMAMK0 0 0 0 DMAPR02 DMAPR01 DMAPR00
FFFFF172H DMAIC1 DMAIF1 DMAMK1 0 0 0 DMAPR12 DMAPR11 DMAPR10
FFFFF174H DMAIC2 DMAIF2 DMAMK2 0 0 0 DMAPR22 DMAPR21 DMAPR20
FFFFF176H DMAIC3 DMAIF3 DMAMK3 0 0 0 DMAPR32 DMAPR31 DMAPR30
FFFFF178H KRIC KRIF KRMK 0 0 0 KRPR2 KRPR1 KRPR0
FFFFF17AH WTIIC WTIIF WTIMK 0 0 0 WTIPR2 WTIPR1 WTIPR0
FFFFF17CH WTIC WTIF WTMK 0 0 0 WTPR2 WTPR1 WTPR0
19.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3)
The IMR0 to IMR3 registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMR0 to
IMR3 registers is equivalent to the xxICn.xxMKn bit.
The IMRm register can be read or written in 16-bit units (m = 0 to 3).
If the higher 8 bits of the IMRm register are used as an IMRmH register and the lower 8 bits as an IMRmL register,
these registers can be read or written in 8-bit or 1-bit units (m = 0 to 3).
Reset sets these registers to FFFFH.
Caution The device file defines the xxICn.xxMKn bit as a reserved word. If a bit is manipulated using the
name of xxMKn, the contents of the xxICn register, instead of the IMRm register, are rewritten (as a
result, the contents of the IMRm register are also rewritten).