Datasheet

V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 651 of 870
Sep 30, 2010
19.3.4 Interrupt control register (xxICn)
The xxICn register is assigned to each interrupt request signal (maskable interrupt) and sets the control conditions for
each maskable interrupt request.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 47H.
Caution Disable interrupts (DI) or mask the interrupt to read the xxICn.xxIFn bit. If the xxIFn bit is read while
interrupts are enabled (EI) or while the interrupt is unmasked, the correct value may not be read
when acknowledging an interrupt and reading the bit conflict.
xxIFn
Interrupt request not issued
Interrupt request issued
xxIFn
0
1
Interrupt request flag
Note
xxICn xxMKn 0 0 0 xxPRn2 xxPRn1 xxPRn0
Interrupt servicing enabled
Interrupt servicing disabled (pending)
xxMKn
0
1
Interrupt mask flag
Specifies level 0 (highest).
Specifies level 1.
Specifies level 2.
Specifies level 3.
Specifies level 4.
Specifies level 5.
Specifies level 6.
Specifies level 7 (lowest).
xxPRn2
0
0
0
0
1
1
1
1
Interrupt priority specification bit
xxPRn1
0
0
1
1
0
0
1
1
xxPRn0
0
1
0
1
0
1
0
1
After reset: 47H R/W Address: FFFFF110H to FFFFF1A8H
<6><7>
Note The flag xxlFn is reset automatically by the hardware if an interrupt request signal is acknowledged.
Remark xx: Identification name of each peripheral unit (see Table 19-2 Interrupt Control Register (xxICn))
n: Peripheral unit number (see Table 19-2 Interrupt Control Register (xxICn)).
The addresses and bits of the interrupt control registers are as follows.