Datasheet

V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 644 of 870
Sep 30, 2010
19.3 Maskable Interrupts
Maskable interrupt request signals can be masked by interrupt control registers. The V850ES/JG3 has 55 maskable
interrupt sources.
If two or more maskable interrupt request signals are generated at the same time, they are acknowledged according to
the default priority. In addition to the default priority, eight levels of priorities can be specified by using the interrupt control
registers (programmable priority control).
When an interrupt request signal has been acknowledged, the acknowledgment of other maskable interrupt request
signals is disabled and the interrupt disabled (DI) status is set.
When the EI instruction is executed in an interrupt service routine, the interrupt enabled (EI) status is set, which
enables servicing of interrupts having a higher priority than the interrupt request signal in progress (specified by the
interrupt control register). Note that only interrupts with a higher priority will have this capability; interrupts with the same
priority level cannot be nested.
To enable multiple interrupts, however, save EIPC and EIPSW to memory or general-purpose registers before
executing the EI instruction, and execute the DI instruction before the RETI instruction to restore the original values of
EIPC and EIPSW.
19.3.1 Operation
If a maskable interrupt occurs, the CPU performs the following processing, and transfers control to a handler routine.
<1> Saves the restored PC to EIPC.
<2> Saves the current PSW to EIPSW.
<3> Writes an exception code to the lower halfword of ECR (EICC).
<4> Sets the PSW. ID bit to 1 and clears the PSW. EP bit to 0.
<5> Sets the handler address corresponding to each interrupt to the PC, and transfers control.
The maskable interrupt request signal masked by INTC and the maskable interrupt request signal generated while
another interrupt is being serviced (while the PSW.NP bit = 1 or the PSW.ID bit = 1) are held pending inside INTC. In this
case, servicing a new maskable interrupt is started in accordance with the priority of the pending maskable interrupt
request signal if either the maskable interrupt is unmasked or the NP and ID bits are cleared to 0 by using the RETI or
LDSR instruction.
How maskable interrupts are serviced is illustrated below.