Datasheet

V850ES/JG3 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
R01UH0015EJ0300 Rev.3.00 Page 641 of 870
Sep 30, 2010
19.2.1 Operation
If a non-maskable interrupt request signal is generated, the CPU performs the following processing, and transfers
control to the handler routine.
<1> Saves the restored PC to FEPC.
<2> Saves the current PSW to FEPSW.
<3> Writes exception code (0010H, 0020H) to the higher halfword (FECC) of ECR.
<4> Sets the PSW.NP and PSW.ID bits to 1 and clears the PSW.EP bit to 0.
<5> Sets the handler address (00000010H, 00000020H) corresponding to the non-maskable interrupt to the PC, and
transfers control.
The servicing configuration of a non-maskable interrupt is shown below.
Figure 19-2. Servicing Configuration of Non-Maskable Interrupt
PSW.NP
FEPC
FEPSW
ECR.FECC
PSW.NP
PSW.EP
PSW.ID
PC
Restored PC
PSW
0010H, 0020H
1
0
1
00000010H,
00000020H
1
0
NMI input
Non-maskable interrupt request
Interrupt servicing
Interrupt request held pending
INTC
acknowledged
CPU processing