Datasheet

V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER)
R01UH0015EJ0300 Rev.3.00 Page 634 of 870
Sep 30, 2010
(12) Read values of DSAn and DDAn registers
Values in the middle of updating may be read from the DSAn and DDAn registers during DMA transfer (n = 0 to 3).
For example, if the DSAnH register and then the DSAnL register are read when the DMA transfer source address
(DSAn register) is 0000FFFFH and the count direction is incremental (DADCn.SAD1 and DADCn.SAD0 bits = 00),
the value of the DSAn register differs as follows, depending on whether DMA transfer is executed immediately
after the DSAnH register is read.
(a) If DMA transfer does not occur while DSAn register is read
<1> Read value of DSAnH register: DSAnH = 0000H
<2> Read value of DSAnL register: DSAnL = FFFFH
(b) If DMA transfer occurs while DSAn register is read
<1> Read value of DSAnH register: DSAnH = 0000H
<2> Occurrence of DMA transfer
<3> Incrementing DSAn register: DSAn = 00100000H
<4> Read value of DSAnL register: DSAnL = 0000H