Datasheet

V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER)
R01UH0015EJ0300 Rev.3.00 Page 633 of 870
Sep 30, 2010
(8) Bus arbitration for CPU
Because the DMA controller has a higher priority bus mastership than the CPU, a CPU access that takes place
during DMA transfer is held pending until the DMA transfer cycle is completed and the bus is released to the CPU.
However, the CPU can access the internal ROM, and internal RAM to/from which DMA transfer is not being
executed.
• The CPU can access the internal ROM and internal RAM when DMA transfer is being executed between the
external memory and on-chip peripheral I/O.
• The CPU can access the internal ROM when DMA transfer is being executed between the on-chip peripheral I/O
and internal RAM.
(9) Registers/bits that must not be rewritten during DMA operation
Set the following registers at the following timing when a DMA operation is not under execution.
[Registers]
• DSAnH, DSAnL, DDAnH, DDAnL, DBCn, and DADCn registers
• DTFRn.IFCn5 to DTFRn.IFCn0 bits
[Timing of setting]
• Period from after reset to start of the first DMA transfer
• Time after channel initialization to start of DMA transfer
• Period from after completion of DMA transfer (TCn bit = 1) to start of the next DMA transfer
(10) Be sure to set the following register bits to 0.
• Bits 14 to 10 of DSAnH register
• Bits 14 to 10 of DDAnH register
• Bits 15, 13 to 8, and 3 to 0 of DADCn register
• Bits 6 to 3 of DCHCn register
(11) DMA start factor
Do not start two or more DMA channels with the same start factor. If two or more channels are started with the
same factor, DMA for which a channel has already been set may be started or a DMA channel with a lower priority
may be acknowledged earlier than a DMA channel with a higher priority. The operation cannot be guaranteed.