Datasheet

V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER)
R01UH0015EJ0300 Rev.3.00 Page 630 of 870
Sep 30, 2010
18.13 Cautions
(1) Caution for VSWC register
When using the DMAC, be sure to set an appropriate value, in accordance with the operating frequency, to the
VSWC register.
When the default value (77H) of the VSWC register is used, or if an inappropriate value is set to the VSWC register,
the operation is not correctly performed (for details of the VSWC register, see 3.4.8 (1) (a) System wait control
register (VSWC)).
(2) Caution for DMA transfer executed on internal RAM
When executing the following instructions located in the internal RAM, do not execute a DMA transfer that transfers
data to/from the internal RAM (transfer source/destination), because the CPU may not operate correctly afterward.
• Bit manipulation instruction located in internal RAM (SET1, CLR1, or NOT1)
• Data access instruction to misaligned address located in internal RAM
Conversely, when executing a DMA transfer to transfer data to/from the internal RAM (transfer source/destination),
do not execute the above two instructions.
(3) Caution for reading DCHCn.TCn bit (n = 0 to 3)
The TCn bit is cleared to 0 when it is read, but it is not automatically cleared even if it is read at a specific timing.
To accurately clear the TCn bit, add the following processing.
(a) When waiting for completion of DMA transfer by polling TCn bit
Confirm that the TCn bit has been set to 1 (after TCn bit = 1 is read), and then read the TCn bit three more
times.
(b) When reading TCn bit in interrupt servicing routine
Execute reading the TCn bit three times.