Datasheet

V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) R01UH0015EJ0300 Rev.3.00 Page 629 of 870 Sep 30, 2010
Figure 18-4. Period in Which DMA Transfer Request Is Ignored (2)
Preparation
for transfer
Read Write
Idle
End
processing
Write
End
processing
Preparation
for transfer
Read
Idle
<1> <2> <3> <4>
CPU processing DMA0 processing CPU processing DMA1 processing CPU processing
Preparation
for transfer
Read
DMA0 transfer request
System clock
DMA1 transfer request
DMA2 transfer request
DMA transfer
Mode of processing
DF0 bit
DF1 bit
DF2 bit
DMA0
processing
<1> DMA0 transfer request
<2> New DMA0 transfer request is generated during DMA0 transfer.
→ A DMA transfer request of the same channel is ignored during DMA transfer.
<3> Requests for DMA0 and DMA1 are generated at the same time.
→ DMA0 request is ignored (a DMA transfer request of the same channel during transfer is ignored).
→ DMA1 request is acknowledged.
<4> Requests for DMA0, DMA1, and DMA2 are generated at the same time.
→ DMA1 request is ignored (a DMA transfer request of the same channel during transfer is ignored).
→ DMA0 request is acknowledged according to priority. DMA2 request is held pending (transfer of DMA2 occurs next).