Datasheet

V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER)
R01UH0015EJ0300 Rev.3.00 Page 628 of 870
Sep 30, 2010
Figure 18-3. Period in Which DMA Transfer Request Is Ignored (1)
Preparation
for transfer
Read cycle
Write cycle
Idle
End
processing
DMA transfer
Mode of processing
DFn bit
System clock
Transfer request generated
after this can be acknowledged
DMA0 processing CPU processingCPU processing
Note 2 Note 2
DMAn transfer
request
Note 1
Note 2
Notes 1. Interrupt from on-chip peripheral I/O, or software trigger (STGn bit)
2. New DMA request of the same channel is ignored between when the first request is generated and
the end processing is complete.
Remark In the case of transfer between external memory spaces (multiplexed bus, no wait)