Datasheet

V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) R01UH0015EJ0300 Rev.3.00 Page 627 of 870 Sep 30, 2010
Figure 18-2. Priority of DMA (2)
Preparation
for transfer
Read
Write
Idle
DMA0 transfer request
System clock
DMA1 transfer request
DMA2 transfer request
DMA transfer
Mode of processing
DF0 bit
DF1 bit
DF2 bit
CPU processing
DMA0 processing CPU processing
DMA1 processing
CPU processing
DMA0
processing
Read
Write
Idle
End
processing
Read
Preparation
for transfer
Preparation
for transfer
End
processing
Remarks 1. Transfer in the order of DMA0 → DMA1 → DMA0 (DMA2 is held pending.)
2. In the case of transfer between external memory spaces (multiplexed bus, no wait)