Datasheet

V850ES/JG3 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER)
R01UH0015EJ0300 Rev.3.00 Page 625 of 870
Sep 30, 2010
18.10 DMA Abort Factors
DMA transfer is aborted if a bus hold occurs.
The same applies if transfer is executed between the internal memory/on-chip peripheral I/O and internal memory/on-
chip peripheral I/O.
When the bus hold is cleared, DMA transfer is resumed.
18.11 End of DMA Transfer
When DMA transfer has been completed the number of times set to the DBCn register and when the DCHCn.Enn bit is
cleared to 0 and TCn bit is set to 1, a DMA transfer end interrupt request signal (INTDMAn) is generated for the interrupt
controller (INTC) (n = 0 to 3).
The V850ES/JG3 does not output a terminal count signal to an external device. Therefore, confirm completion of DMA
transfer by using the DMA transfer end interrupt or polling the TCn bit.
18.12 Operation Timing
Figures 18-1 to 18-4 show DMA operation timing.